Semiconductor Supply Chains

By the end of this lesson, you will be able to...

• Trace a chip from design through fabrication, assembly, test, and delivery.

• Identify the upstream inputs that each stage needs in order to continue.

• Distinguish a supply-chain bottleneck from a strategic chokepoint.

Idea in one sentence: A chip is not made in one place; it becomes usable only when several specialized stages and their inputs arrive in the right order.

Core Insight

Imagine that a public-transport supplier needs 500,000 control chips for a new fleet of electric buses. The chip design is finished. The buyer has a contract with a well-known chip company. The obvious story is simple: the company will make the chips and deliver them.

That story hides the mechanism.

The design needs specialist software and reusable design components. A fabrication plant needs equipment, wafers, chemicals, gases, spare parts, power, water, and a production slot. The finished wafer still contains many individual pieces of silicon, not ready-to-install chips. Those pieces must be cut, connected, protected in a package, tested, moved through logistics, placed on boards, and delivered to the bus supplier.

If one necessary stage cannot provide enough suitable output in time, the bus project can be delayed even while every other stage is working well.

This is why semiconductor supply chains matter to technology geopolitics. The strategic question is not only "Who owns a chip brand?" It is "Which actors, inputs, and capabilities must keep working for this specific chip to reach its user?"

The Small Situation

The bus supplier, Meridian Transit, needs a custom controller that manages battery charging and safety checks. It has ordered 500,000 completed chips for delivery in nine months.

Meridian sees only two direct partners:

• Orbit Design, which designed the controller;
• Harbor Systems, which will place the chips on circuit boards for the buses.

Orbit does not operate a semiconductor factory. It sends the design to a contract manufacturer. The contract manufacturer sends completed wafers to a separate company that assembles, tests, and packages the chips. Harbor Systems receives only the finished packaged chips.

At first, Meridian treats Orbit as the whole supply chain because that is the name on its contract. This is understandable. Contracts create a visible boundary.

But the physical dependency chain crosses that boundary. The real question is whether each hidden handoff can produce the required quantity, quality, and schedule.

The Moving Parts

Semiconductor production is too complex to learn as a single straight factory line. A useful first map has three main production stages and several critical inputs.

A fab is a semiconductor fabrication facility. A foundry is a manufacturer that fabricates chips for external design customers. A design firm that creates chips but outsources fabrication is often called fabless.

Plain meaning:

Each stage turns an unfinished input into something the next stage can use.

In Meridian's case:

Orbit turns a control requirement into a chip design. The foundry turns that design into patterned wafers. The assembly/test provider turns wafer pieces into tested, protected chips. Harbor turns chips into bus control boards.

Technical name:

This sequence is a semiconductor value chain. It includes the direct stages and the specialized suppliers that make those stages possible.

The map is deliberately simple. Real chips vary greatly. Some use different materials, several dies in one package, or unusual testing and qualification steps. The point is not to memorize every process. The point is to see that a chip's apparent origin is often a network of distinct capabilities.

The Mechanism Step by Step

Return to Meridian's controller. The requested output is not a design file or a wafer. It is 500,000 tested, packaged chips that Harbor can mount on a board.

1. Design and handoff

Orbit chooses the controller's functions, validates the design, and combines its own work with licensed building blocks such as communication or memory interfaces. It uses electronic-design automation software to check whether the design can be manufactured and tested.

When the design is ready, Orbit sends the manufacturing data to the foundry. This handoff is commonly called tape-out.

Tape-out does not create a chip. It commits a design to a particular manufacturing process and starts a chain of expensive, time-sensitive work.

2. Wafer fabrication

The foundry reserves production time. It processes silicon wafers through repeated operations that place patterns and materials on the wafer. This step depends on highly specialized equipment and materials. It also depends on stable operation: a tool outage, contaminated input, or missing replacement part can affect output.

At the end, the wafer contains many copies of Meridian's controller. They are still attached to the wafer and have not yet become finished components for a bus.

3. Assembly, test, and packaging

The wafer is cut into individual pieces called dies. A provider connects each die to a package, protects it, and tests whether it performs within the required limits. The package is not decorative. It provides the electrical and physical connection between the silicon and the board that will use it.

This stage is often shortened to ATP: assembly, test, and packaging. When a separate contractor performs it for customers, the contractor is often called an OSAT, for outsourced semiconductor assembly and test.

4. Integration and qualification

Harbor receives packaged chips, mounts them on boards, loads firmware, and tests the board in the bus-control system. A chip that passed a generic factory test can still fail a customer's particular qualification, for example because its behavior with the chosen board or environment is not acceptable.

Only after these handoffs does Meridian have the thing it ordered: usable controller capacity in buses.

A Worked Trace: Where Did the 500,000 Chips Go?

Assume the numbers below are a teaching model, not an industry forecast. Real yields differ by chip, process, package, and maturity.

Meridian needs 500,000 tested controllers. Orbit asks the foundry to begin with enough potential die to cover normal losses.

The naive response is: "The fab made the chips, so the order is complete."

The trace shows why that is wrong. Fabrication output is not customer-ready output. The shortfall appears only after the required downstream stages have done their work.

Now add a second pressure. The ATP provider has enough staff and machines, but its packaging-substrate supplier delays a compatible substrate. Wafers are ready. The foundry is not the current constraint. Yet finished chips cannot move through the next stage at the planned rate.

Meridian has several possible responses:

1. wait for the substrate and delay bus production;
2. pay for priority allocation if the supplier can offer it;
3. qualify a second package or provider;
4. redesign the package;
5. use a temporary controller only if the system can safely accept one.

Each response has a cost. A second source is not a switch that flips instantly. The alternative may need compatible tooling, engineering work, customer testing, regulatory evidence, or a new contract. A redesign can improve future resilience while making the current schedule worse.

So far, we have seen a chain rather than a single factory. The buyer's useful supply is limited by the narrowest necessary stage, adjusted for time and qualification. The visible chip seller may be important, but it is rarely the only actor that matters.

Bottleneck, Chokepoint, and Substitute

A bottleneck is any necessary step with too little capacity for the required demand. Meridian's delayed substrate is a bottleneck if it prevents the ATP provider from completing enough packages on time.

A chokepoint is a stronger claim. A bottleneck becomes strategically important when an actor controls a dependency that is hard to replace, alternatives are slow or unsuitable, and interruption would materially change another actor's choices.

This distinction prevents two mistakes:

• calling every busy supplier a chokepoint;
• ignoring a quiet, highly specialized input because it is small or unfamiliar.

To test a possible chokepoint, ask:

1. Is this input necessary for the target chip or workload?
2. How concentrated is supply or capability?
3. Are qualified substitutes available before the deadline?
4. Who controls access, service, licensing, or allocation?
5. What happens to the downstream user if access stops?

The answer may change with the chip. A substitute suitable for a simple consumer device may be unusable for transit, medical, industrial, or defense equipment because certification and reliability requirements differ.

Cost, Limits, and Signals

Specialization creates real benefits. A design firm can focus on architecture. A foundry can spread the cost of difficult fabrication across many customers. An ATP provider can build deep expertise in packaging and test. This division of labor can make better chips available at lower cost.

It also creates coordination pressure. More handoffs mean more dependencies, more schedules, and more places where a change must be qualified. Building every stage inside one organization can reduce some external dependencies, but it costs large amounts of capital, talent, time, and continuing demand. Vertical integration is not a free escape from risk; it replaces some supplier risk with internal operating risk.

This model helps when a buyer needs to reason about a specific chip, product, or capability. It does not predict exactly where the next disruption will occur. A chain can be resilient to one failure and fragile to another.

Useful signals include:

• lead times and order backlog by stage;
• sole-source tools, materials, IP blocks, or package types;
• yield changes and test failures;
• inventory of qualified inputs rather than generic inventory alone;
• capacity allocation rules and cancellation terms;
• time and evidence required to qualify an alternative;
• repair lead times for equipment and spare parts.

These signals make a supply-chain map operational. Instead of saying "chips are scarce," an analyst can say which input is constrained, which product depends on it, how long substitution takes, and what decision should change.

Common Confusions

Confusion: The country of the brand tells us where the chip is made

Why it is tempting:

The brand, contract, and final product label are easy to see.

Better model:

Design, wafer fabrication, packaging, test, equipment, materials, and final integration can be performed by different firms in different places. Trace the functions before making an origin claim.

Confusion: Packaging happens after the important technical work

Why it is tempting:

The silicon circuit feels like the "real" chip.

Better model:

Packaging and test turn a die into a component that can connect to a system and meet performance requirements. They can affect schedule, reliability, and capability, and they can become a binding constraint.

Confusion: Two suppliers mean immediate resilience

Why it is tempting:

Two names on a supplier list look like a backup plan.

Better model:

Resilience depends on whether the second source is technically compatible, contractually available, qualified for the product, and able to supply in time. Nominal alternatives may share the same upstream dependency.

Check Your Understanding

Check: A buyer has a domestic design firm, but its chosen foundry, packaging provider, and substrate supplier are elsewhere. Which statement is best?

Think first, then reveal.

Answer: The buyer has domestic design capability but a distributed production chain. This is neither automatically safe nor automatically fragile. The next step is to map which external inputs are necessary, how quickly they can be substituted, and what interruption would affect the buyer's goal.

Check: Wafers are on schedule, but final test rejects more chips than expected. Which part of the trace should the analyst inspect first?

Think first, then reveal.

Answer: Inspect assembly, test, and packaging yield, along with the package and test conditions. The problem may be downstream of wafer fabrication, so increasing fab output alone might not repair the shortage.

Practice

A medical-device company needs 120,000 sensor chips for a product launch. Its map shows:

• a design firm can finish the design on time;
• the foundry has a production slot for 150,000 potential die;
• expected fabrication yield is 90%;
• the only qualified packaging provider can package 100,000 chips before the launch date;
• a second packaging provider exists, but qualification would take six months;
• the product launch is four months away.

Answer these questions:

1. What is the immediate bottleneck?
2. Is the second provider an effective substitute for this launch? Why or why not?
3. Which evidence would you request before deciding whether the packaging provider is a strategic chokepoint?
4. Name one response and one trade-off.

A good answer identifies packaging capacity as the immediate bottleneck: even if fabrication yields 135,000 working die, only 100,000 can become qualified packaged chips before launch. The second provider is not an effective substitute inside the four-month deadline. To assess chokepoint risk, ask about supply concentration, control of allocation, shared upstream materials or equipment, qualification options, and the effect of a missed launch. A response could delay the launch, prioritize a smaller product batch, begin second-source qualification, or redesign the package. Each costs time, revenue, engineering effort, or current flexibility.

Resources

• [REPORT] Mapping the Semiconductor Value Chain — Focus: Use the 2025 map to distinguish design, fabrication, assembly/test/packaging, and their specialized inputs.
• [REPORT] Vulnerabilities in the Semiconductor Supply Chain — Focus: Trace how upstream software, materials, and equipment connect to downstream electronic products.
• [REPORT] Results from Semiconductor Supply Chain Request for Information — Focus: Compare generic inventory with actual capacity, material, and assembly/test/packaging constraints.

Key Takeaways

• A semiconductor supply chain is a sequence of specialized transformations, not one company or one factory.
• A finished wafer is not yet a customer-ready chip; assembly, test, packaging, and downstream qualification are necessary stages.
• A bottleneck is a necessary step with insufficient timely capacity. A chokepoint additionally involves hard substitution, meaningful control, and material consequences of interruption.
• Specialization can improve cost and performance while creating dependencies that require coordination and qualification.
• A useful map names the target chip, its required stages and inputs, the available substitutes, the time to switch, and the decision affected by a disruption.